byCHARME 2001 (2001 : Livingston, Scotland); Margaria-Steffen, Tiziana, 1964-; Melham, T. F. (Tom F.)
Correct Hardware Design and Verification Methods: 11th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2001 Livingston, Scotland, UK, September 4–7, 2001 Proceedings Author: Tiziana Margaria, Tom Melham Published by Springer Berlin Heidelberg ISBN: 978-3-540-42541-0 DOI: 10.1007/3-540-44798-9 Table of Contents: View from the Fringe of the Fringe Hardware Synthesis Using SAFL and Application to Processor Design Applications of Hierarchical Verification in Model Checking Pruning... Topics: Integrated circuits, Integrated circuits
Professional Verification: A Guide to Advanced Functional Verification Author: Paul Wilcox Published by Springer US ISBN: 978-1-4020-7875-0 DOI: 10.1007/b118052 Table of Contents: Introduction Verification Challenges Advanced Funtional Verification Successful Verification Professional Verification The Unified Verification Methodology UVM System-Level Design Control Digital Subsystems Algorithmic Digital Subsystems Analog/RF Subsystems Integration and System Verification System-Level Design... Topics: Integrated circuits, Integrated circuits
Correct Hardware Design and Verification Methods: 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L’Aquila, Italy, October 21-24, 2003. Proceedings Author: Daniel Geist, Enrico Tronci Published by Springer Berlin Heidelberg ISBN: 978-3-540-20363-6 DOI: 10.1007/b93958 Table of Contents: What Is beyond the RTL Horizon for Microprocessor and System Design? The Charme of Abstract Entities The PSL/Sugar Specification Language A Language for all Seasons Finding Regularity:... Topics: Integrated circuits, Integrated circuits
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design Author: Fan Mo, Robert K. Brayton Published by Springer US ISBN: 978-1-4020-8040-1 DOI: 10.1007/b117043 Table of Contents: Introduction Preliminaries Circuit Structures Block-Level Placement and Routing The Module-Based Design Flow Conclusion Topic: Integrated circuits
The Mullard FJ range of integrated circuits uses transistor-transistor logic (TTL). In this book, the characteristics of TTL are explained and, to enable engineers to use the FJ range of TTL integrated circuits. Topics: Mullard, integrated circuits, TTL
Book digitized by Google from the library of Harvard University and uploaded to the Internet Archive by user tpb. Topic: Linear integrated circuits Source: http://books.google.com/books?id=8MsMAAAAYAAJ&oe=UTF-8
byFMCAD 2000 (2000 : Austin, Tex.); Hunt, Warren A., 1958-; Johnson, Steven D. (Steven Dexter)
Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 Proceedings Author: Warren A. Hunt Jr., Steven D. Johnson Published by Springer Berlin Heidelberg ISBN: 978-3-540-41219-9 DOI: 10.1007/3-540-40922-X Table of Contents: Applications of Hierarchical Verification in Model Checking Trends in Computing A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon An Algorithm... Topics: Computer engineering, Integrated circuits
byIEEE/ACM International Conference on Computer-Aided Design; Kuehlmann, Andreas
The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design Author: Andreas Kuehlmann Published by Springer US ISBN: 978-1-4613-5007-1 DOI: 10.1007/978-1-4615-0292-0 Table of Contents: Formal Methods for Functional Verification Automating the Diagnosis and the Rectification of Design Errors with PRIAM Functional Comparison of Logic Designs for VLSI Circuits A Unified Framework for the Formal Verification of Sequential Circuits Dynamic Variable Ordering for Ordered Binary Decision... Topics: Integrated circuits, Computer-aided design, Computer-aided design, Integrated circuits
Advanced Verification Techniques: A SystemC Based Approach for Successful Tapeout Author: Leena Singh, Leonard Drucker, Neyaz Khan Published by Springer US ISBN: 978-1-4020-7672-5 DOI: 10.1007/b105272 Table of Contents: Introduction Verification Process Using SCV for Verification Functional Verification Testplan Testbench Concepts using SystemC Verification Methodology Regression/Setup and Run Functional Coverage Dynamic Memory Modeling Post Synthesis Gate Simulation Topics: Integrated circuits, TECHNOLOGY & ENGINEERING, TECHNOLOGY & ENGINEERING, Integrated circuits
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation 10th International Workshop,PATMOS 2000 Göttingen, Germany, September 13–15, 2000 Proceedings Author: Dimitrios Soudris, Peter Pirsch, Erich Barke Published by Springer Berlin Heidelberg ISBN: 978-3-540-41068-3 DOI: 10.1007/3-540-45373-3 Table of Contents: Constraints, Hurdles and Opportunities for a Successful European Take-Up Action Architectural Design Space Exploration Achieved through Innovative RTL Power... Topics: Integrated circuits, Computer-aided design
Timing Author: Sachin Sapatneka Published by Springer US ISBN: 978-1-4020-7671-8 DOI: 10.1007/b117318 Table of Contents: Preduction/Introface A Quick Overview of Circuit Simulation Frequency-Domain Analysis of Linear Systems Timing Analysis for a Combinational Stage Timing Analysis for Combinational Circuits Statistical Static Timing Analysis Timing Analysis for Sequential Circuits Transistor-Level Combinational Timing Optimization Clocking and Clock Skew Optimization Retiming Conclusion Topics: Timing circuits, Integrated circuits, Time-series analysis
Languages for System Specification: Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specification from FDL’03 Author: Christoph Grimm Published by Springer US ISBN: 978-1-4020-7990-0 DOI: 10.1007/b116586 Table of Contents: UML-Based Co-Design for Run-Time Reconfigurable Architectures A Unified Approach to Code Generation from Behavioral Diagrams Platform-Independent Design for Embedded Real-Time Systems Real-Time System Modeling with ACCORD/UML... Topics: Computer hardware description languages, Integrated circuits
Design and Analysis of High Efficiency Line Drivers for xDSL Author: Tim Piessens, Michiel Steyaert Published by Springer US ISBN: 978-1-4020-7727-2 DOI: 10.1007/b105290 Table of Contents: Introduction XDSL Line Drivers: Signals, Specifications and Traditional Solutions Describing Function Analysis Behavioural Modelling of Self Oscillating Power Amplifiers High-Level Design Plan Synthesis and CAD-Techniques for Non-Linear SOPA Design Realisations in Mainstream CMOS Conclusions Topics: Digital subscriber lines, Line drivers (Integrated circuits)
byReis, Ricardo A. L. (Ricardo Augusto da Luz); Jess, Jochen
Design of System on a Chip: Devices & Components Author: Ricardo Reis, Jochen A. G. Jess Published by Springer US ISBN: 978-1-4020-7928-3 DOI: 10.1007/b116432 Table of Contents: Design of Systems on a Chip: Introduction BJT Modeling with VBIC A MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation Efficient Statistical Modeling for Circuit Simulation Retargetable Application-driven Analog-digital Block Design Robust Low Voltage Low Power Analog Mos VLSI Design... Topics: Integrated circuits, Systems on a chip
Power-constrained Testing of VLSI Circuits Author: Nicola Nicolici, Bashir M. Al-Hashimi Published by Springer US ISBN: 978-1-4020-7235-2 DOI: 10.1007/b105922 Table of Contents: Design and Test of Digital Integrated Circuits Power Dissipation During Test Approaches to Handle Test Power Power Minimization Based on Best Primary Input Change Time Test Power Minimization Using Multiple Scan Chains Power-conscious Test Synthesis and Scheduling Power Profile Manipulation Conclusion Topics: Integrated circuits, Very large scale integration, Integrated circuits, Very large scale...
SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits Author: Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau Published by Springer US ISBN: 978-1-4020-7837-8 DOI: 10.1007/b117058 Table of Contents: Introduction Survey of Previous Work Models and Representations Our Parallelizing High-Level Synthesis Methodology Pre-Synthesis Compiler Optimizations Compiler and Synthesis Transformations Employed During Scheduling Code Transformations and Scheduling... Topics: SPARK (Electronic resource), Digital integrated circuits, Digital integrated circuits, Parallel...
byMehrotra, Amit; Sangiovanni-Vincentelli, Alberto
Noise Analysis of Radio Frequency Circuits Author: Amit Mehrotra, Alberto Sangiovanni-Vincentelli Published by Springer US ISBN: 978-1-4419-5404-6 DOI: 10.1007/978-1-4757-6007-1 Table of Contents: Introduction Overview of Existing Techniques Perturbation Analysis of Stable Oscillators Noise Analysis of Stable Oscillators Noise Analysis of Nonautonomous Circuits Noise Analysis of Circuits with Multitone Inputs Noise Analysis of Phase-Locked Loops Conclusions and Future Directions Topics: Radio frequency integrated circuits, Electronic noise, Electronic noise, Radio frequency integrated...
Formal Methods in Computer-Aided Design: Second International Conference, FMCAD’ 98 Palo Alto, CA, USA, November 4–6, 1998 Proceedings Author: Ganesh Gopalakrishnan, Phillip Windley Published by Springer Berlin Heidelberg ISBN: 978-3-540-65191-8 DOI: 10.1007/3-540-49519-3 Table of Contents: Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution Bit-Level... Topics: Digital integrated circuits, Automatic theorem proving, Integrated circuits, Computer engineering,...
Verification by Error Modeling: Using Testing Techniques in Hardware Verification Author: Katarzyna Radecka, Zeljko Zilic Published by Springer US ISBN: 978-1-4020-7652-7 DOI: 10.1007/b105974 Table of Contents: Introduction Boolean Function Representations Don’t Cares and Their Calculation Testing Design Error Models Design Verification by At Identifying Redundant Gate and Wire Replacements Conclusions and Future Work Topics: Integrated circuits, Error analysis (Mathematics), Error analysis (Mathematics)
byInternational Conference on Evolvable Systems (4th : 2001 : Tokyo, Japan); Liu, Yong, 1966-
Evolvable Systems: From Biology to Hardware: 4th International Conference, ICES 2001 Tokyo, Japan, October 3–5, 2001 Proceedings Author: Yong Liu, Kiyoshi Tanaka, Masaya Iwata, Tetsuya Higuchi, Moritoshi Yasunaga Published by Springer Berlin Heidelberg ISBN: 978-3-540-42671-4 DOI: 10.1007/3-540-45443-8 Table of Contents: Two-Step Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates Untidy Evolution: Evolving Messy Gates for Fault Tolerance Evolutionary Design... Topics: Evolutionary programming (Computer science), Evolutionary computation, Digital integrated circuits
Process variation is an difficulty in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common trans conductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We further apply our scheme to two well known amplifier topologies in the sun-micron CMOS process as design examples—an inductive degenerated low-noise... favorite ( 2 reviews ) Topics: CMOS analog integrated circuits, process compensation, process variation, self-biasing.